1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices and, more specifically, to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs (central processing units), storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a planar device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate structure positioned above the channel region. These elements are sometimes referred to as the source, drain, channel and gate, respectively. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NMOS device, if there is no voltage applied to the gate electrode, then there is no current flow through the NMOS device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and prevent the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. The FinFET device may have either a tri-gate or a dual gate channel structure. In a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current density than planar transistor devices.
Another form of 3D semiconductor device employs so-called nanowire structures for the channel region of the device. There are several known techniques for forming such nanowire structures. As the name implies, at the completion of the fabrication process, the nanowire structures typically have a generally circular cross-sectional configuration. Nanowire devices are considered to be one option for solving the constant and continuous demand for semiconductor devices with smaller feature sizes. However, the manufacture of nanowire devices is a very complex process. However, it is believed that, for nanowire devices to be useful in producing production integrated circuit devices, such a nanowire device must include a plurality of stacked nanowires, e.g., three or more, such that the device can generate an acceptable level of drive current. Forming such tall, stacked nanowire structures can be very challenging for many reasons.
Irrespective of whether a planar or non-planar device is considered, electrical connections must be formed to the device so that it may operate as intended. That is, electrical connections must be made to the source region, the drain region and the gate electrode of the device. Typically, the conductive structures that actually make contact with the device itself, i.e., the source region, the drain region and the gate electrode, are referred to as “contacts” within the industry. Such conductive contacts are formed in one or more layers of insulating material. The entire arrangement of the conductive contacts and the associated layer(s) of insulating material are sometimes referred to as the “contact level” of the overall electrical “wiring arrangement” that is formed to provide electrical connection to the integrated circuit device.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. A modern integrated circuit product will typically comprise several metallization layers, e.g., multiple layers of conductive vias and conductive lines. The M1 metallization layer is typically the first major “wiring” layer that is formed on the product. As device dimensions have decreased, the conductive contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the source/drain regions of the transistors, thereby providing self-aligned trenches which are substantially laterally delineated by the spacer structures of the gate electrode structures.
Notwithstanding the complex processing described above, device dimensions continue to decrease and packing densities continue to increase. For gate pitch scaling less than, for example, 50 nm, there is simply not enough space for the formation of the gate contact, the source contact and the drain contact using existing methodologies and traditional devices, e.g., planar devices. Thus, nanowire devices present a potentially attractive alternative to obtained the desired control of the gate (so as to avoid or at least reduce undesirable short channel effects) and to reduce the gate length of the transistor device, so as to thereby leave more room for the formation of the various source, drain and gate contacts. However, even with such scaled nanowire devices, the source/drain regions are very small in terms of area. Typically, an epi semiconductor material will be formed in the source/drain regions of the device and, thereafter, a metal silicide region will be formed on the epi material so as to reduce the contact resistance when forming a conductive contact to the source/drain region. Given the very small contact area available in the source/drain region, the resulting metal silicide region also has a corresponding small contract area, which means an undesirable increase in the contact resistance. Such an increase in contact resistance can result in the degradation of the performance of the device.
The present disclosure is directed to various methods of forming conductive contact structures for a semiconductor device with a larger metal silicide contact area and the resulting devices that may reduce or eliminate one or more of the problems identified above.